The present invention relates generally to error-correcting code (ECC) decoders, and, more particularly, to a Bose-Chaudhuri-Hochquenghem (BCH) decoder.
The memory industry has witnessed a rise in the use of embedded static random access memory (SRAM) and multi-level NAND/NOR flash memory devices that are used in functional safety systems of automotive, industrial, and health care applications. The rise may be attributed primarily to the memory size versus cost advantage offered by such devices. However, the NAND/NOR flash memory devices are less reliable than other memory types (viz., embedded SRAM and other flash memories) and are prone to soft errors in which the bits stored in such memories are flipped. The reliability is further reduced when the memories are operated in an environment that is exposed to high-energy cosmic rays, alpha, and solar particles, causing an increased incidence of soft errors.
The critical nature of functional safety systems requires them to have fault tolerant and resilient architectures and to be compliant with safety standards including ISO 26262 and IEC 61508. Since these memory devices are prone to errors, error-correcting codes (ECCs) are used to ensure compliance with the safety standards. ECCs ensure detection and correction of the data stored in the memory and include Hamming codes, Reed-Solomon (R-S) codes, Bose-Chaudhuri-Hochquenghem (BCH) codes, circular redundancy check codes (CRC), Golay codes, Reed-Muller codes, Goppa codes, and Denniston codes.
BCH ECCs are a popular class of codes used to detect and correct soft errors. Their popularity stems from the relatively simple encoding and decoding processes used by the BCH ECCs. However, like other ECCs, the BCH ECC decoding process is much more complicated than the encoding process and involves execution of a time consuming algorithm generally performed with specialized hardware, i.e., a BCH decoder. The complexity of the decoding algorithm increases with an increase in a count of bit errors that can be corrected by the ECC, which translates into a more complicated design of the BCH decoder. The increase in design complexity increases the silicon area required by the BCH decoder as well as the processing time, which leads to increased cost.
Therefore, it would be advantageous to have a BCH decoder that has a simpler implementation, requires less silicon area, and operates faster, and that overcomes the above-mentioned limitations of conventional BCH decoders.